Understanding the interfacial layer formation on strained Si1-xGex channels and their correlation to inversion layer hole mobility
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2017
- VLSI Technology 2017
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32 results for Ruqiang Bao
Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2017
- ASICON 2017
Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition
- Anuja De Silva
- Indira Seshadri
- et al.
- 2017
- J. Micro/Nanolithogr. MEMS MOEMS
Development of TiO2 containing hardmasks through PEALD deposition
- Anuja De Silva
- Indira Seshadri
- et al.
- 2017
- SPIE Advanced Lithography 2017
Hot carrier effect in ultra-scaled replacement metal gate Sii-xGex channel p-FinFETs
- Miaomiao Wang
- X. Miao
- et al.
- 2016
- IEDM 2016
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
Selective GeOx-scavenging from interfacial layer on Si1-xGex channel for high mobility Si/Si1-xGex CMOS application
- Choonghyun Lee
- H. Kim
- et al.
- 2016
- VLSI Technology 2016
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
- Dechao Guo
- G. Karve
- et al.
- 2016
- VLSI Technology 2016
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014