Fluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
Publications
15 results for Carl Radens
1.5-V single work-function W/WN/n+-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- Rajesh Rengarajan
- Boyong He
- et al.
- 2002
- IEEE Electron Device Letters
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998