Maciel Zortea, Miguel Paredes, et al.
IGARSS 2021
Significant challenges face DRAM scaling toward and beyond the 0.10-μm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.
Maciel Zortea, Miguel Paredes, et al.
IGARSS 2021
S.M. Sadjadi, S. Chen, et al.
TAPIA 2009
Rajeev Gupta, Shourya Roy, et al.
ICAC 2006
Israel Cidon, Leonidas Georgiadis, et al.
IEEE/ACM Transactions on Networking