A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
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45 results for Jose A. Tierno
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- Jean-Olivier Plouchart
- Mihai Sanduleanu
- et al.
- 2012
- CICC 2012
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
- Ankur Agrawal
- John Bulzacchelli
- et al.
- 2012
- ISSCC 2012
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
- Sameh Asaad
- Ralph Bellofatto
- et al.
- 2012
- FPGA 2012
Indirect phase noise sensing for self-healing voltage controlled oscillators
- S. Yaldiz
- V. Calayir
- et al.
- 2011
- CICC 2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
- Jae-Sun Seo
- Bernard Brezzo
- et al.
- 2011
- CICC 2011
Adaptive energy-management features of the IBM POWER7 chip
- Michael Floyd
- Malcolm Ware
- et al.
- 2011
- IBM J. Res. Dev
IBM POWER7 processor circuit design
- Dieter Wendel
- John Barth
- et al.
- 2011
- IBM J. Res. Dev