A 28 GHz hybrid PLL in 32 nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2014
- IEEE JSSC
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45 results for Jose A. Tierno
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
Asynchronous parallel prefix computation
- Rajit Manohar
- José A. Tierno
- 1998
- IEEE TC
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2014
- CICC 2014
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
A 28GHz hybrid PLL in 32nm SOI CMOS
- Mark Ferriss
- Alexander Rylyakov
- et al.
- 2013
- VLSI Circuits 2013
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- Jean-Olivier Plouchart
- Mihai Sanduleanu
- et al.
- 2012
- CICC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012