An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz
- Montek Singh
- Jose A. Tierno
- et al.
- 2002
- ASYNC 2002
Publications
Date
Featured collections
Popular topics
45 results for Jose A. Tierno
Improved Performance of 10 Gb/s Multimode Fiber Optic Links Using Equalization
- P. Pepeljugoski
- J. Schaub
- et al.
- 2002
- OFC 2002
Asynchronous circuits and systems in superconducting RSFQ digital technology
- Z. John Deng
- Nobuyoki Yoshikawa
- et al.
- 1998
- ASYNC 1998
Asynchronous transpose-matrix architectures
- J. Tierno
- Prabhakar Kudva
- 1997
- ICCD 1997
The energy and entropy of VLSI computations
- J. Tierno
- R. Manohar
- et al.
- 1996
- ASYNC 1996
Indirect performance sensing for on-chip self-healing of analog and RF circuits
- Shupeng Sun
- Fa Wang
- et al.
- 2014
- IEEE TCAS-I
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
Adaptive energy-management features of the IBM POWER7 chip
- Michael Floyd
- Malcolm Ware
- et al.
- 2011
- IBM J. Res. Dev
IBM POWER7 processor circuit design
- Dieter Wendel
- John Barth
- et al.
- 2011
- IBM J. Res. Dev
An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz
- Montek Singh
- Jose A. Tierno
- et al.
- 2010
- IEEE Transactions on VLSI Systems