0.026μm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
- C. Pei
- G. Wang
- et al.
- 2014
- IEDM 2014
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11 results for Daniel Jaeger
2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- Dechao Guo
- Kathryn Schonenberg
- et al.
- 2009
- MRS Fall Meeting 2009
Effect of germanium preamorphization implant on performance and gate-induced drain leakage in SiGe channel pFET
- Vishal A. Tiwari
- Young Way Teh
- et al.
- 2015
- IEEE Electron Device Letters
Single wafer cleaning lessons in advanced node gate module development
- David F. Hilscher
- Daniel Jaeger
- et al.
- 2013
- ASMC 2013
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008