Design and optimization of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology
- You Li
- Rahul Mishra
- et al.
- 2015
- EOS/ESD 2015
Publications
Date
Featured collections
Popular topics
22 results for You Li
3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015
Junction engineering for SOI SCR triggering and performance improvement
- You Li
- Junjun Li
- et al.
- 2014
- EOS/ESD 2014
ESD device performance analysis in a 14nm Fin FET SOI CMOS technology: Fin-based versus planar-based
- Junjun Li
- Robert Gauthier
- et al.
- 2014
- EOS/ESD 2014
Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network
- You Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
Investigation of SOI SCR triggering and current sustaining under DC and TLP conditions
- Junjun Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013
High performance bulk planar 20nm CMOS technology for low power mobile applications
- Huiling Shang
- Sameer Jain
- et al.
- 2012
- VLSI Technology 2012
Reduction of RTA-driven intra-die variation via model-based layout optimization
- J.C. Scott
- O. Gluschenkov
- et al.
- 2009
- VLSI Technology 2009
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008