High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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22 results for You Li
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
3D integration ESD protection design and analysis
- Souvick Mitra
- Ephrem Gebreselasie
- et al.
- 2015
- EOS/ESD 2015
Design and optimization of ESD lateral NPN device in 14nm Fin FET SOI CMOS technology
- You Li
- Rahul Mishra
- et al.
- 2015
- EOS/ESD 2015
Junction engineering for SOI SCR triggering and performance improvement
- You Li
- Junjun Li
- et al.
- 2014
- EOS/ESD 2014
ESD device performance analysis in a 14nm Fin FET SOI CMOS technology: Fin-based versus planar-based
- Junjun Li
- Robert Gauthier
- et al.
- 2014
- EOS/ESD 2014
Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network
- You Li
- James Di Sarro
- et al.
- 2013
- EOS/ESD 2013