Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2007
- IRPS 2007
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35 results for Robert Gauthier
Design and characterization of a multi-rc-triggered MOSFET-based power clamp for on-chip ESD protection
- Junjun Li
- Robert Gauthier
- et al.
- 2006
- EOS/ESD 2006
Analysis of failure mechanism on gate-silicided and gate-non-silicided, drain/source silicide-blocked ESD NMOSFETs in a 65nm bulk CMOS technology
- Junjun Li
- David Alvarez
- et al.
- 2006
- IPFA 2006
Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2006
- IRPS 2006
PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness
- Junjun Li
- Robert Gauthier
- et al.
- 2005
- EOS/ESD 2005
VF-TLP systems using TDT and TDRT for Kelvin wafer measurements and package level testing
- Evan Grund
- Robert Gauthier
- 2004
- EOS/ESD 2004
A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection
- Junjun Li
- Robert Gauthier
- et al.
- 2004
- EOS/ESD 2004
I/O interface latchup analysis using optical and electrical testing
- Franco Stellari
- Peilin Song
- et al.
- 2004
- Electronic Device Failure Analysis
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
- K. Chatty
- P.E. Cottrell
- et al.
- 2004
- IRPS 2004
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
- K. Chatty
- P.E. Cottrell
- et al.
- 2004
- IRPS 2004