Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- VLSI Technology 2011
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29 results for A. Bryant
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- Chung-Hsun Lin
- Wilfried Haensch
- et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm2 SRAM cell
- Kangguo Cheng
- A. Khakifirooz
- et al.
- 2011
- VLSI Circuits 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- Tenko Yamashita
- Veeraraghvan S. Basker
- et al.
- 2011
- CSTIC 2011
Non-planar device architecture for 15nm node: FinFET or trigate?
- Chung-Hsun Lin
- Josephine Chang
- et al.
- 2010
- IEEE International SOI Conference 2010
FinFET resistance mitigation through design and process optimization
- Cindy Wang
- Josephine Chang
- et al.
- 2009
- VLSI-TSA 2009
FinFET performance advantage at 22nm: An AC perspective
- M. Guillorn
- J. Chang
- et al.
- 2008
- VLSI Technology 2008
Simulation study of multiple FIN FinFET design for 32nm technology node and beyond
- Xinlin Wang
- Andres Bryant
- et al.
- 2007
- SISPAD 2007
Energy optimality and variability in subthreshold design
- Scott Hanson
- Bo Zhai
- et al.
- 2006
- ISLPED 2006