Publications

18 results for J. Faltermeier

Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- - Isaac Lauer
  - Nicolas Loubet
  - et al.
- 2015
- VLSI Technology 2015
Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
- - K. Cheng
  - S.-C. Seo
  - et al.
- 2014
- VLSI Technology 2014
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- - Abhijeet Paul
  - Andres Bryant
  - et al.
- 2013
- IEDM 2013
Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs
- - Abhijeet Paul
  - Chun-Chen Yeh
  - et al.
- 2013
- S3S 2013
Superior PBTI reliability for SOI FinFET technologies and its physical understanding
- - Miaomiao Wang
  - Ramachandran Muralidhar
  - et al.
- 2013
- IEEE Electron Device Letters
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- - Kingsuk Maitra
  - Ali Khakifirooz
  - et al.
- 2011
- IEEE Electron Device Letters
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- - A. Khakifirooz
  - Kangguo Cheng
  - et al.
- 2010
- VLSI-TSA 2010
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010