Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
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18 results for J. Faltermeier
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
- K. Cheng
- A. Khakifirooz
- et al.
- 2009
- VLSI Technology 2009
22 nm technology compatible fully functional 0.1 μm 2 6T-sram cell
- B. Haran
- A. Kumar
- et al.
- 2008
- IEDM 2008
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- B. Yang
- R. Takalkar
- et al.
- 2008
- IEDM 2008
Recent progress and challenges in enabling embedded Si:C technology
- B. Yang
- Z. Ren
- et al.
- 2008
- ECS Meeting 2008
Process and electrical characteristics of MO-ALD HfO2 films for high-K gate applications grown in a production-worthy 300 mm deposition system
- R.D. Clark
- C.S. Wajda
- et al.
- 2007
- ECS Meeting 2007
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
High yielding self-aligned contact-process for a 0.150-μm DRAM technology
- Thomas S. Rupp
- David Dobuzinsky
- et al.
- 2002
- IEEE Trans Semicond Manuf