Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- C. Kothandaraman
- X. Chen
- et al.
- 2015
- IRPS 2015
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23 results for D. Moy
Technology elements of a common platform bulk foundry offering (invited)
- P. Gilbert
- A. Steegen
- et al.
- 2007
- IEDM 2007
Reliability investigation of NiPtSi electrical fuse with different programming mechanisms
- C. Tian
- D. Moy
- et al.
- 2007
- IIRW 2007
A compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
- Norm Robson
- John Safran
- et al.
- 2007
- CICC 2007
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Optimization of resolution-enhanced photolithography for a 256Mb DRAM cell
- R. Ferguson
- Christopher P. Ausschnitt
- et al.
- 1994
- VLSI Technology 1994
The application of deep UV phase shifted-single layer halftone reticles to 256 mbit dynamic random access memory cell patterns
- Kohji Hashimoto
- Donald J. Samuels
- et al.
- 1994
- Japanese Journal of Applied Physics
High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply
- Y. Taur
- S.J. Wind
- et al.
- 1993
- IEDM 1993
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993