Optimization of resolution-enhanced photolithography for a 256Mb DRAM cell
- R. Ferguson
- Christopher P. Ausschnitt
- et al.
- 1994
- VLSI Technology 1994
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23 results for D. Moy
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993
A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography
- D. Moy
- L.K. Wang
- et al.
- 1990
- VLSI Technology 1990
Electromigration in a two-level Al-Cu interconnection with W studs
- T. Kwok
- C. Tan
- et al.
- 1990
- VMIC 1990
Two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM
- D. Moy
- M. Schadt
- et al.
- 1989
- VMIC 1989
0. 5 MICRON GATE CMOS TECHNOLOGY USING E-BEAM/OPTICAL MIX LITHOGRAPHY.
- L.K. Wang
- Y. Taur
- et al.
- 1985
- VLSI Technology 1985
The application of deep UV phase shifted-single layer halftone reticles to 256 mbit dynamic random access memory cell patterns
- Kohji Hashimoto
- Donald J. Samuels
- et al.
- 1994
- Japanese Journal of Applied Physics
Highly selective sputtering of silicon from TiSi2 at elevated temperature
- J.M.E. Harper
- S. Motakef
- et al.
- 1992
- Applied Physics Letters
A High-Performance 0.25-μm CMOS Technology: II—Technology
- Bijan Davari
- Wen-Hsing Chang
- et al.
- 1992
- IEEE T-ED
Novel self-aligned W/TiN/TiSi2 contact structure for very shallow junctions and interconnections
- R.V. Joshi
- D. Moy
- et al.
- 1989
- Applied Physics Letters