Two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM

Abstract

Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. A structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti/Al(2.5%Cu)/Si metal lines patterned by reactive ion etching. This structure has been successfully implemented both on BEOL test sites and in device runs to fabricate a selectively scaled 0.5-μm-channel-length 64-kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal to or better than that achieved with metal lift-off processing. Functional testing of the 64-kb SRAM produced many chips with better than 90% yield, which is also equal to or better than that achieved with a nonplanarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2. No degradation of device characteristics due to the BEOL processing could be detected.