High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Publications
Date
Featured collections
Popular topics
26 results for B. Jagannathan
22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
Leakage engineering enabling PDSOI ring oscillators operating in sub-100pA/μm Ioff regime
- Zhibin Ren
- Jin Cai
- et al.
- 2011
- CSTIC 2011
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- A. Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- VLSI-TSA 2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2010
- ISSCC 2010
RF modeling of 45nm low-power CMOS technology
- Jing Wang
- Hongmei Li
- et al.
- 2009
- NSTI-Nanotech 2009
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007
Experimental analysis of on-wafer de-embedding techniques for RF modeling of advanced RFCMOS and BiCMOS technologies
- Jing Wang
- Robert Groves
- et al.
- 2007
- ARFTG 2007
RF characterization and parameter extraction for CMOS device models
- John J. Pekarik
- Basanth Jagannathan
- et al.
- 2007
- SiRF 2007