Publications

28 results for D. Schepis

High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Deposited ALD SiO₂ high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- - S. Siddiqui
  - M.M. Chowdhury
  - et al.
- 2013
- ECS Meeting 2013
Observation of semiconductor device channel strain using in-line high resolution X-ray diffraction
- - Judson R. Holt
  - Anita Madan
  - et al.
- 2013
- Journal of Applied Physics
High performance bulk planar 20nm CMOS technology for low power mobile applications
- - Huiling Shang
  - Sameer Jain
  - et al.
- 2012
- VLSI Technology 2012
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- - D.-G. Park
  - K. Stein
  - et al.
- 2009
- VLSI-TSA 2009
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- - B. Yang
  - R. Takalkar
  - et al.
- 2008
- IEDM 2008
Recent progress and challenges in enabling embedded Si:C technology
- - B. Yang
  - Z. Ren
  - et al.
- 2008
- ECS Meeting 2008
Effect of ion implantation and anneals on fully-strained SiC and SiC:P films using multiple characterization techniques
- - A. Madan
  - J. Li
  - et al.
- 2008
- ECS Meeting 2008
Channel Strain Characterization in Embedded SiGe by Nano-beam Diffraction
- - J. Li
  - A. Lamberti
  - et al.
- 2008
- ECS Meeting 2008