Publications

23 results for D.-G. Park

High-performance CMOS-compatible self-aligned In_0.53Ga_0.47As MOSFETs with GMSAT over 2200 μs/μm at V_DD = 0.5 v
- - Yanning Sun
  - Amlan Majumdar
  - et al.
- 2014
- IEDM 2014
Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution
- - Y. Sun
  - A. Majumdar
  - et al.
- 2013
- IEDM 2013
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- - Zhibin Ren
  - S. Mehta
  - et al.
- 2011
- IEDM 2011
Full metal gate with borderless contact for 14 nm and beyond
- - Soon-Cheon Seo
  - L.F. Edge
  - et al.
- 2011
- VLSI Technology 2011
Effective schottky barrier lowering for contact resistivity reduction using silicides as diffusion sources
- - Zhen Zhang
  - F. Pagette
  - et al.
- 2010
- VLSI-TSA 2010
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Copper contact metallization for 22 nm and beyond
- - Soon-Cheon Seo
  - Chih-Chao Yang
  - et al.
- 2009
- IITC 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- - K. Henson
  - H. Bu
  - et al.
- 2008
- IEDM 2008
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- - B. Yang
  - R. Takalkar
  - et al.
- 2008
- IEDM 2008