Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Publications
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23 results for Kisik Choi
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
The past, present and future of high-k/metal gates
- Kisik Choi
- Takashi Ando
- et al.
- 2013
- ECS Meeting 2013
Origins of effective work function roll-off behavior for high-κ last replacement metal gate stacks
- Takashi Ando
- Eduard A. Cartier
- et al.
- 2013
- IEEE Electron Device Letters
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012
Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- IEDM 2011
Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011
Mechanism of VFB / VTH shift in Dysprosium incorporated HfO2 gate dielectric n-Type Metal-Oxide-Semiconductor devices
- Tackhwi Lee
- Kisik Choi
- et al.
- 2011
- Journal of Vacuum Science and Technology B
Origin of the flatband-voltage roll-off phenomenon in metal/high-k gate stacks
- Gennadi Bersuker
- Chang Seo Park
- et al.
- 2010
- IEEE T-ED