A novel integration scheme for self-aligend Ru topvia as post-Cu alternative metal interconnects
- K. Motoyama
- D. Metzler
- et al.
- 2023
- IITC/MAM 2023
Publications
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23 results for Kisik Choi
Overlay Performance in Permanent Bonded Wafer Integration Schemes
- Nathan Ip
- Michael Belyansky
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
BEOL compatible high-capacitance MIMCAP structure using a novel high k material
- P. Jamison
- John Massey
- et al.
- 2020
- IMCS 2020
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
The past, present and future of high-k/metal gates
- Kisik Choi
- Takashi Ando
- et al.
- 2013
- ECS Meeting 2013
Bias temperature instability in high-κ/metal gate transistors - Gate stack scaling trends
- Siddarth Krishnan
- Vijay Narayanan
- et al.
- 2012
- IRPS 2012
Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011
Ultimate EOT scaling (< 5Å) using Hf-based high-κ gate dielectrics and impact on carrier mobility
- Takashi Ando
- Martin M. Frank
- et al.
- 2010
- ECS Transactions
Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond
- K. Choi
- H. Jagannathan
- et al.
- 2009
- VLSI Technology 2009
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- Chris Penny
- Koichi Motoyama
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024