Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Publications
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23 results for Kisik Choi
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- IEDM 2011
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t-tuning dipoles with gate-first process
- T. Ando
- M.M. Frank
- et al.
- 2009
- IEDM 2009
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
- Nicholas A. Lanzillo
- Kisik Choi
- et al.
- 2019
- IEEE Electron Device Letters
Origins of effective work function roll-off behavior for high-κ last replacement metal gate stacks
- Takashi Ando
- Eduard A. Cartier
- et al.
- 2013
- IEEE Electron Device Letters
A novel single damascene process for via metal corrosion-free interconnects in advanced nodes
- Koichi Motoyama
- Dominik Metzler
- et al.
- 2024
- IITC 2024