High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
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20 results for Hasan M Nayfeh
(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004
Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport Model
- Hasan M. Nayfeh
- Judy L. Hoyt
- et al.
- 2003
- IEDM 2003
Increasing Quantum Volume on a superconducting quantum computing system
- Petar Jurcevic
- Ali Javadi
- et al.
- 2021
- APS March Meeting 2021
Evidence for the utility of quantum computing before fault tolerance
- Youngseok Kim
- Andrew Eddins
- et al.
- 2023
- Nature
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
- H. Nayfeh
- D. Singh
- et al.
- 2006
- IEEE Electron Device Letters
Impact of source/drain contact and gate finger spacing on the RF reliability of 45-nm RF nMOSFETs
- Rajan Arora
- Sachin Seth
- et al.
- 2011
- IRPS 2011