Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
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15 results for C. Durfee
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology
- Oleg Gluschenkov
- Heng Wu
- et al.
- 2018
- IEDM 2018
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
SiGe Gate-All-around Nanosheet Reliability
- Huimei Zhou
- Miaomiao Wang
- et al.
- 2022
- IRPS 2022
OCD enhanced: Implementation and validation of spectral interferometry for nanosheet inner spacer indentation
- Daniel Schmidt
- C. Durfee
- et al.
- 2021
- SPIE Advanced Lithography 2021
In-line Raman spectroscopy for stacked nanosheet device manufacturing
- Daniel Schmidt
- C. Durfee
- et al.
- 2021
- SPIE Advanced Lithography 2021