Scaling opportunities for Gate-All-Around: A patterning perspective
- I. Seshadri
- E. Miller
- et al.
- 2023
- IEDM 2023
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25 results for A. Greene
Contact Cavity Shaping and Selective SiGe:B Low-Temperature Epitaxy Process Solution for sub 10-9 Ω.cm2 Contact Resistivity in Nonplanar FETs
- N. Breil
- B.-C. Lee
- et al.
- 2023
- VLSI Technology 2023
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Vertical Travelling Scatterometry for Metrology on Fully Integrated Devices
- D. Schmidt
- Manasa Medikonda
- et al.
- 2022
- SPIE Advanced Lithography 2022
OCD enhanced: Implementation and validation of spectral interferometry for nanosheet inner spacer indentation
- Daniel Schmidt
- C. Durfee
- et al.
- 2021
- SPIE Advanced Lithography 2021
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020