Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
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15 results for J. Frougier
High Performance Nanosheet Technology Optimized for 77 K
- R. Bao
- L. Qin
- et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around: A patterning perspective
- I. Seshadri
- E. Miller
- et al.
- 2023
- IEDM 2023
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Vertical Travelling Scatterometry for Metrology on Fully Integrated Devices
- D. Schmidt
- Manasa Medikonda
- et al.
- 2022
- SPIE Advanced Lithography 2022
OCD enhanced: Implementation and validation of spectral interferometry for nanosheet inner spacer indentation
- Daniel Schmidt
- C. Durfee
- et al.
- 2021
- SPIE Advanced Lithography 2021
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Development of SiGe Indentation Process Control to Enable Stacked Nanosheet FET Technology
- Dexin Kong
- Daniel Schmidt
- et al.
- 2020
- ASMC 2020