Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
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75 results for Juntao Li
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019
SiGe Channel CMOS: Understanding Dielectric Breakdown and Bias Temperature Instability Tradeoffs
- Richard G. Southwick
- Miaomiao Wang
- et al.
- 2019
- VLSI Technology 2019
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019
Channel Strain Dependence of Tinv in Strained Si and Sil-xGexFETs: Internal Strain-induced Modification of Chemical Oxidation
- Choonghyun Lee
- Shogo Mochizuki
- et al.
- 2019
- VLSI Technology 2019
Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si
- Choonghyun Lee
- Richard G. Southwick
- et al.
- 2018
- IEDM 2018
Leakage aware Si/SiGe CMOS FinFET for low power applications
- G. Tsutsui
- C. Durfee
- et al.
- 2018
- VLSI Technology 2018
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Impact of Liner Metals on Copper Resistivity at beyond 7nm Dimensions
- H. Huang
- Nicholas A. Lanzillo
- et al.
- 2018
- IITC 2018