Veeraraghvan S. Basker, Theodorus E. Standaert, et al.
VLSI Technology 2010
We combine advanced transmission electron microscopy (TEM) and numerical models to draw the evolution of strains over the integration of horizontally stacked Gate-All-Around Nanosheet transistors (GAANS). In particular, we measured compressive strains of -0.5% to -1% after channel release in transistors at 10 nm design rule. With support on model calculations, we speculate that the effect is related to a compressive inter-layer dielectric (ILD). As another method to manipulate channel stresses, in a specifically designed GAANS we demonstrate a transition from compressive to tensile strain introduced by a gate stack/contact test modules. Finally, a demonstration of GAANS Si-channel cladded with SiGe opens a way for the co-integration of compressive SiGe channels with limited modification of the integration flow. The findings provide insights and guidelines for strain engineering in GAANS.