Resistivity of copper interconnects at 28 nm pitch and copper cross-sectional area below 100 nm2
- Adam Pyzyna
- Hsinyu Tsai
- et al.
- 2017
- IITC 2017
Publications
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76 results for Eric A. Joseph
Evaluation of ALE processes for patterning
- J. M. Papalia
- Nathan Marchack
- et al.
- 2016
- SPIE Advanced Lithography 2016
High chi block copolymer DSA to improve pattern quality for FinFET device fabrication
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2016
- SPIE Advanced Lithography 2016
Resistivity of copper interconnects beyond the 7 nm node
- Adam Pyzyna
- Robert L. Bruce
- et al.
- 2015
- VLSI Technology 2015
Moving from thin films to atomic layers - Atomic layer etching
- Craig Huffman
- Eric A. Joseph
- et al.
- 2015
- VLSI-TSA 2015
Self-aligned line-space pattern customization with directed self-assembly graphoepitaxy at 24nm pitch
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2015
- SPIE Advanced Lithography 2015
Subtractive W contact and local interconnect co-integration (CLIC)
- Fei Liu
- Benjamin Fletcher
- et al.
- 2013
- IITC 2013
A scalable volume-confined phase change memory using physical vapor deposition
- S.C. Lai
- S. Kim
- et al.
- 2013
- VLSI Technology 2013
Recovery dynamics and fast (sub-50ns) read operation with Access Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC)
- G.W. Burr
- K. Virwani
- et al.
- 2013
- VLSI Technology 2013
Advanced plasma etch for the 10nm node and beyond
- Eric Joseph
- Sebastian Engelmann
- et al.
- 2013
- SPIE Advanced Lithography 2013