A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
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18 results for Lawrence Pileggi
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
- S. Sun
- F. Wang
- et al.
- 2013
- CICC 2013
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
Post-silicon calibration of analog CMOS using phase-change memory cells
- Cheng-Yuan Wen
- Jeyanandh Paramesh
- et al.
- 2011
- ESSCIRC 2011
Indirect phase noise sensing for self-healing voltage controlled oscillators
- S. Yaldiz
- V. Calayir
- et al.
- 2011
- CICC 2011
A non-volatile look-up table design using PCM (phase-change memory) cells
- Cheng-Yuan Wen
- J. Li
- et al.
- 2011
- VLSI Circuits 2011
Modeling interconnect variability using efficient parametric model order reduction
- Peng Li
- Frank Liu
- et al.
- 2005
- DATE 2005
Circuit Simulation of Nanotechnology Devices with Non-monotonie I-V Characteristics
- Jiayong Le
- Larry Pileggi
- et al.
- 2003
- ICCAD 2003
Regular logic fabrics for a via patterned gate array (VPGA)
- K.Y. Tong
- V. Kheterpal
- et al.
- 2003
- CICC 2003