Advanced FDSOI design: The U-channel device for 7nm node and beyond
- Ramachandran Muralidhar
- Robert Dennard
- et al.
- 2017
- S3S 2017
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36 results for Isaac Lauer
Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
- Seong-Dong Kim
- Michael Guillorn
- et al.
- 2015
- S3S 2015
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- Isaac Lauer
- Nicolas Loubet
- et al.
- 2015
- VLSI Technology 2015
Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications
- Hsin-Yu Tsai
- Hiroyuki Miyazoe
- et al.
- 2013
- SPIE Advanced Lithography 2013
Channel doping impact on FinFETs for 22nm and beyond
- Chung-Hsun Lin
- R. Kambhampati
- et al.
- 2012
- VLSI Technology 2012
A 0.021 μm2 trigate SRAM cell with aggressively scaled gate and contact pitch
- Michael A. Guillorn
- Josephine Chang
- et al.
- 2011
- VLSI Technology 2011
Sub-20 nm abrupt USJ formation with long ms-flash with sub-2 nm dopant motion control
- Kam-Leung Lee
- Isaac Lauer
- et al.
- 2010
- IWJT 2010
Are Si/SiGe tunneling field-effect transistors a good idea?
- Steven J. Koester
- Isaac Lauer
- et al.
- 2010
- ECS Transactions
Low power circuit design based on heterojunction tunneling transistors (HETTs)
- Daeyeon Kim
- Yoonmyung Lee
- et al.
- 2009
- ISLPED 2009
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
- Elbert Huang
- Eric Joseph
- et al.
- 2008
- IEEE International SOI Conference 2008