CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
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48 results for Mukesh Khare
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability
- Noah Zamdmer
- Jonghae Kim
- et al.
- 2004
- VLSI Technology 2004
Dual layer SrTiO3/HfO2 gate dielectric for aggressively scaled band-edge nMOS devices
- C. Choi
- E. Cartier
- et al.
- 2007
- Microelectronic Engineering
Optimization of silicon technology for the IBM System z9
- Daniel J. Poindexter
- Scott R. Stiffler
- et al.
- 2007
- IBM J. Res. Dev
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power mmWave digital and RF circuit capability
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2005
- IEEE Transactions on Electron Devices
Thickness measurement of ultra-thin gate dielectrics under inversion condition
- W. Zhu
- Mukesh Khare
- et al.
- 2001
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings