High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
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48 results for Mukesh Khare
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power mmWave digital and RF circuit capability
- Jean-Olivier Plouchart
- Noah Zamdmer
- et al.
- 2005
- IEEE Transactions on Electron Devices
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability
- Noah Zamdmer
- Jonghae Kim
- et al.
- 2004
- VLSI Technology 2004
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Thickness measurement of ultra-thin gate dielectrics under inversion condition
- W. Zhu
- Mukesh Khare
- et al.
- 2001
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999