A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- Peter J. Klim
- John Barth
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
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22 results for Subramanian Iyer
Analysis of retention time distribution of embedded DRAM - A new mMethod to characterize across-chip threshold voltage variation
- W. Kong
- P. Parries
- et al.
- 2008
- IEEE ITC 2008
A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications
- Chengwen Pei
- Roger Booth
- et al.
- 2008
- ICSICT 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
An investigation of electrical current induced phase transformations in the NiPtSi/polysilicon system
- Deok-Kee Kim
- Anthony Domenicucci
- et al.
- 2008
- Journal of Applied Physics
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- John Barth
- William R. Reohr
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Beyond scaling - Teaching the old dog some new tricks!
- Subramanian S. Iyer
- 2007
- IPFA 2007
A compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006