Characterization of random process variations using ultralow-power, high-sensitivity, bias-free sub-threshold process sensor
- Mesut Meterelliyoz
- Peilin Song
- et al.
- 2010
- IEEE TCAS-I
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44 results for Kaushik Roy
A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm CMOS
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs
- Jing Li
- Aditya Bansal
- et al.
- 2008
- ACM JETC
Optimal dual-VT design in sub-100-nm PD/SOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Poly-Si thin-film transistors: An efficient and low-cost option for digital operation
- Jing Li
- Aditya Bansal
- et al.
- 2007
- IEEE Transactions on Electron Devices
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal
Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS
- Saibal Mukhopadhyay
- Keejong Kim
- et al.
- 2007
- IEEE Journal of Solid-State Circuits
Device-optimization technique for robust and low-power FinFET SRAM design in NanoScale era
- Aditya Bansal
- Saibal Mukhopadhyay
- et al.
- 2007
- IEEE Transactions on Electron Devices
Modeling and analysis of leakage currents in double-gate technologies
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems