A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
Publications
Date
Featured collections
Popular topics
56 results for M. Wordeman
Process-design considerations for three dimensional memory integration
- S.S. Iyer
- T. Kirihata
- et al.
- 2009
- VLSI Technology 2009
Destructive-read Random Access Memory System Buffered with Destructive-read Memory Cache for SoC Applications
- Brian L. Ji
- Seiji Munetoh
- et al.
- 2003
- VLSI Circuits 2003
Development of a high bandwidth merged logic/DRAM multimedia chip
- W.K. Luk
- Y. Katayama
- et al.
- 1997
- ICCD 1997
Flexible test mode design for DRAM characterization
- H. Wong
- T. Kirihata
- et al.
- 1996
- VLSI Circuits 1996
170 nm gates fabricated by phase-shift mask and top anti-reflector process
- T.A. Brunner
- P.N. Sanda
- et al.
- 1993
- Microlithography 1993
Hot-carrier induced instability of 0.5 μm CMOS devices patterned using synchrotron X-ray lithography
- C.C.-H. Hsu
- L.K. Wang
- et al.
- 1989
- IRPS 1989
0.5 μm CMOS device design and characterization
- H.I. Hanafi
- M.R. Wordeman
- et al.
- 1987
- ESSDERC 1987
FULLY SEALED HALF-MICROMETER NMOS TECHNOLOGY USING DIRECT-WIRE E-BEAM LITHOGRAPHY.
- M.R. Wordeman
- A.M. Schweighart
- et al.
- 1983
- VLSI Technology 1983
One-Micron Polycide (WSI2 on Poly-Si) MOSFET Technology
- M.Y. Tsai
- H.H. Chao
- et al.
- 2019
- JES