Toshiaki Kirihata, Hing Wong, et al.
IEEE Journal of Solid-State Circuits
This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm2 256 Mb DRAM with ×32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 μA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield. © 1996 IEEE.
Toshiaki Kirihata, Hing Wong, et al.
IEEE Journal of Solid-State Circuits
Brian L. Ji, Seiji Munetoh, et al.
VLSI Circuits 2003
Toshiaki Kirihata, John Golz, et al.
IEEE JESTCS
John Safran, Alan Leslie, et al.
VLSI Circuits 2007