A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
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63 results for J. Demarest
Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology
- Hiroaki Niimi
- Zuoguang Liu
- et al.
- 2016
- IEEE Electron Device Letters
Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
Process Challenge in Analog Computing Hardware using Phase Change Memory (PCM)
- Victor Chan
- I. Ok
- et al.
- 2023
- ASMC 2023
Impact of Nanosecond Laser Anneal on PVD Ru Films
- D. Sil
- Yasir Sulehria
- et al.
- 2021
- IITC 2021
Selective deposition of AlOx for Fully Aligned Via in nano Cu interconnects
- Son Van Nguyen
- Hosadurga Shobha
- et al.
- 2021
- IITC 2021
Middle of Line (MOL) Process Investigation in Ring Oscillator failure
- Victor Chan
- M. Bergendahl
- et al.
- 2020
- ASMC 2020
Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019