Chip Power-Frequency Scaling in 10/7nm Node
- Phil Oldiges
- Reinaldo A. Vega
- et al.
- 2020
- IEEE Access
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105 results for Ghavam Shahidi
A Low-Power Thin-Film Si Heterojunction FET Noise Amplifier for Generation of True Random Numbers
- Bahman Hekmatshoar
- Ghavam Shahidi
- 2019
- IEEE J-EDS
Chip Power Scaling in Recent CMOS Technology Nodes
- Ghavam Shahidi
- 2019
- IEEE Access
Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially Grown Emitter/Collector Regions
- Pouya Hashemi
- Jeng-Bang Yau
- et al.
- 2017
- IEEE J-EDS
Inversion mode n -channel GaAs field effect transistor with high- k /metal gate
- J.P. De Souza
- E.W. Kiewra
- et al.
- 2008
- Applied Physics Letters
Optimizing CMOS technology for maximum performance
- David J. Frank
- Wilfried Haensch
- et al.
- 2006
- IBM J. Res. Dev
PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2002
- Journal of Electrostatics
Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips
- S. Voldman
- D. Hui
- et al.
- 2000
- Journal of Electrostatics
Implementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings