Device and circuit design issues in SOI technology
- G. Shahidi
- A. Ajmera
- et al.
- 1999
- CICC 1999
Publications
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188 results for Devendra Sadana
Nondestructive evaluation of interfaces in bonded silicon-on-insulator structures using the picosecond ultrasonics technique
- H.-Y. Hao
- H.J. Maris
- et al.
- 1998
- Electrochemical and Solid-State Letters
CMOS-on-SOI ESD protection networks
- S. Voldman
- R. Schulz
- et al.
- 1998
- Journal of Electrostatics
High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1997
- IEEE Electron Device Letters
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
Formation of ultrathin, buried oxides in Si by O+ ion implantation
- O.W. Holland
- D. Fathy
- et al.
- 1996
- Applied Physics Letters
Suppression of the SOI floating-body effects by linked-body device structure
- W. Chen
- Y. Taur
- et al.
- 1996
- VLSI Technology 1996
History dependence of non-fully depleted (NFD) digital SOI circuits
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- VLSI Technology 1996
0.25μm low power CMOS devices and circuits from 8 inch SOI materials
- B. Chen
- A.S. Yapsir
- et al.
- 1995
- ICSICT 1995
Effect of the back gate conduction on 0.25 μm SOI devices
- J.L. Pelloie
- D.K. Sadana
- et al.
- 1994
- IEDM 1994