CMOS-on-SOI ESD protection networks

Abstract

ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm mainstream CMOS-on-SOI technology. Design layout, body contact, floating-gate effects and novel ESD protection implementations are discussed. © 1998 Elsevier Science B.V.