Extending technology roadmap by selective device footprint scaling and parasitics engineering
- Jie Deng
- Lan Wei
- et al.
- 2008
- VLSI-TSA 2008
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51 results for Ching-Te Chuang
On-chip process variation detection using slew-rate monitoring circuit
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2008
- VLSID 2008
Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2008
- IEEE Transactions on Electron Devices
Design and analysis of thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- ISLPED 2007
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
- Ching-Te Chuang
- Saibal Mukhopadhyay
- et al.
- 2007
- MTDT 2007
High-performance device optimization and dual-VT technology options for doublegate FET
- Aditya Bansal
- Keunwoo Kim
- et al.
- 2007
- ICICDT 2007
Asymmetrical SRAM cells with enhanced read and write margins
- Keunwoo Kim
- Jae-Joon Kim
- et al.
- 2007
- VLSI-TSA 2007
Device footprint scaling for ultra thin body fully depleted SOI
- Jie Deng
- Keunwoo Kim
- et al.
- 2007
- ISQED 2007
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2007
- Microelectronics Journal
The impact of device footprint scaling on high-performance CMOS logic technology
- Jie Deng
- Keunwoo Kim
- et al.
- 2007
- IEEE Transactions on Electron Devices