A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
Publications
7 results for Aydin Babakhani
An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
A near-field millimeter-wave dielectric imaging technique with sub-wavelength spatial resolution
- Aydin Babakhani
- Duixian Liu
- et al.
- 2011
- IRMMW-THz 2011
A scalable 6-to-18 GHz concurrent dual-band quad-beam phased-array receiver in CMOS
- Sanggeun Jeon
- Yu-Jiu Wang
- et al.
- 2008
- IEEE Journal of Solid-State Circuits