Bodhisatwa Sadhu, Alberto Valdes-Garcia, et al.
RFIC 2016
An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of-126.5 dBc/Hz at 20.1 GHz and-124.2 dBc/Hz at 24 GHz © 2012 IEEE.
Bodhisatwa Sadhu, Alberto Valdes-Garcia, et al.
RFIC 2016
Alberto Valdes-Garcia, Arun Natarajan, et al.
RFIC 2013
Arun Natarajan, Brian Floyd, et al.
ISSCC 2007
Brian A. Floyd, Alberto Valdes-Garcia, et al.
VLSI-TSA 2010