Optimization of 3nm High Performance Nanosheet Technology for 77 K OperationJulien FrougierRuqiang Baoet al.2025GOMACTech 2025
Novel ellipsometry-based machine learning technique for characterization of low sensitivity critical dimensions within gate-all-around transistorsHoussam ChouaibValeria Dimastrodonatoet al.2024SPIE Advanced Lithography + Patterning 2024
Scaling opportunities for Gate-All-Around and beyond: A patterning perspectiveIndira SeshadriEric Milleret al.2023IEDM 2023
Development of SiGe Indentation Process Control for Gate-All-Around FET Technology EnablementDaniel SchmidtAron Cepleret al.2022IEEE Trans Semicond Manuf
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around TransistorsCurtis DurfeeSubhadeep Kalet al.2021ECS Meeting 2021
Nanosheet Metrology Opportunities for Technology ReadinessMary BretonDaniel Schmidtet al.2021SPIE Advanced Lithography 2021
15 Dec 2025US12501698Stacked Transistors Having Self Aligned Backside Contact With Backside Replacement Metal Gate
Advanced logic technology at 2nm nodePlatform technology research: innovation and solution creation for leading edge CMOS technology at 2nm node.
Introducing the world's first 2 nm node chipNewsJulien Frougier and Dechao Guo06 May 20215 minute readHybrid CloudIntelligent FabLogic ScalingQuantumQuantum SystemsSemiconductors