Novel ellipsometry-based machine learning technique for characterization of low sensitivity critical dimensions within gate-all-around transistors
- Houssam Chouaib
- Valeria Dimastrodonato
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Julien Frougier
Title
Senior Engineer: IBM Semiconductors - Advanced Logic Technology Research
Publications
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Development of SiGe Indentation Process Control for Gate-All-Around FET Technology Enablement
- Daniel Schmidt
- Aron Cepler
- et al.
- 2022
- IEEE Trans Semicond Manuf
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Nanosheet Metrology Opportunities for Technology Readiness
- Mary Breton
- Daniel Schmidt
- et al.
- 2021
- SPIE Advanced Lithography 2021
Patents
- US
- 12183740
- US
- 12176345
- CN
- ZL202180021003.1
- TW
- I864786
- US
- 12154945
- US
- 12154985
- JP
- 7592092
- US
- 12150310
- IN
- 554611
- US
- 12142526
Projects
Platform technology research: innovation and solution creation for leading edge CMOS technology at 2nm node.
Blog posts
Introducing the world's first 2 nm node chip
NewsJulien Frougier and Dechao Guo5 minute read
Top collaborators
DG
Dechao Guo
Director, Advanced Logic Technology R&D
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
NL
Nicolas Loubet
STSM, Advanced Logic Technology Research
MW
Miaomiao Wang
Manager, Reliability