Improving yields of high performance 65 nm chips with sputtering top surface of dual stress liner
- Huilong Zhu
- Daewon Yang
- et al.
- 2007
- VLSI Technology 2007
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63 results for Effendi Leobandung
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
Implementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- Jay Strane
- David Brown
- et al.
- 2007
- VLSI-TSA 2007
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Optimizing history effects in 65nm PD-SOI CMOS
- Q. Liang
- T. Kawamura
- et al.
- 2006
- IEEE International SOI Conference 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Design of a high performance PD SOI for the 0.18 μm technology generation
- M. Sherony
- S.-H. Lo
- et al.
- 2000
- ICM 2000
Partially-depleted SOI compact model - formulation and parameter extraction
- S.K.H. Fung
- L. Wagner
- et al.
- 2000
- VLSI Technology 2000
0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Device and circuit design issues in SOI technology
- G. Shahidi
- A. Ajmera
- et al.
- 1999
- CICC 1999