A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
Publications
68 results for Effendi Leobandung
Improving yields of high performance 65 nm chips with sputtering top surface of dual stress liner
- Huilong Zhu
- Daewon Yang
- et al.
- 2007
- VLSI Technology 2007
(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineering
- B. Yang
- A. Waite
- et al.
- 2007
- IEDM 2007
Implementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- Jay Strane
- David Brown
- et al.
- 2007
- VLSI-TSA 2007
On the control of short-channel effect for MOSFETs with reverse halo implantation
- Huilong Zhu
- Huicai Zhong
- et al.
- 2007
- IEEE Electron Device Letters
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- I. Ahsan
- N. Zamdmer
- et al.
- 2006
- VLSI Technology 2006
Optimizing history effects in 65nm PD-SOI CMOS
- Q. Liang
- T. Kawamura
- et al.
- 2006
- IEEE International SOI Conference 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002