RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology

We report, for the first time, a detailed study of Infra-Die Variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in V T and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities. CMOS, RTA, Variation, and Ramp Rate © 2006 IEEE.