A novel high-performance lateral bipolar on SOI
- G. Shahidi
- D.D. Tang
- et al.
- 1991
- IEDM 1991
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83 results for Yuan Taur
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing
- G. Shahidi
- B. Davari
- et al.
- 1990
- IEDM 1990
A comparative study of hot-carrier instabilities in p- and n-type poly gate MOSFETs
- C.C.-H. Hsu
- D.S. Wen
- et al.
- 1989
- IEDM 1989
A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
- B. Davari
- C. Koburger
- et al.
- 1989
- IEDM 1989
A self-aligned inverse-T gate fully overlapped LDD device for sub-half micron CMOS
- D.S. Wen
- C.C.-H. Hsu
- et al.
- 1989
- IEDM 1989
Variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS
- B. Davari
- C. Koburger
- et al.
- 1988
- IEDM 1988
Doping of n+ and p+ polysilicon in a dual-gate CMOS process
- C.Y. Wong
- J.Y.-C. Sun
- et al.
- 1988
- IEDM 1988
0. 5- mu M-CHANNEL CMOS TECHNOLOGY OPTIMIZED FOR LIQUID-NITROGEN-TEMPERATURE OPERATION.
- J.Y.-C. Sun
- Y. Taur
- et al.
- 1985
- IEDM 1985
HIGHLY LATCHUP-IMMUNE 1- mu m CMOS TECHNOLOGY FABRICATED WITH 1 Mev ION IMPLANTATION AND SELF-ALIGNED TiSi//2.
- F.S. Lai
- L.K. Wang
- et al.
- 1984
- IEDM 1984
CHARACTERIZATION AND MODELING OF A LATCHUP-FREE 1- mu M CMOS TECHNOLOGY.
- Y. Taur
- W.H. Chang
- et al.
- 1983
- IEDM 1983