Pong-Fei Lu, James D. Warnock, et al.
IEEE T-ED
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Pong-Fei Lu, James D. Warnock, et al.
IEEE T-ED
John D. Cressler, Denny D. Tang, et al.
IEEE T-ED
Inanc Meric, Cory R. Dean, et al.
IEDM 2011
C. Zhou, Keith A. Jenkins, et al.
IRPS 2018