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IEEE Electron Device Letters
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Mario M. Pelella, Jerry G. Fossum, et al.
IEEE Electron Device Letters
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Nature Nanotechnology
Cheng-Wei Cheng, Kuen-Ting Shiu, et al.
Nature Communications
Bruce Doris, Meikei Ieong, et al.
IEDM 2002