High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
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22 results for Clement Wann
High performance CMOS bulk technology using direct silicon bond (DSB) mixed crystal orientation substrates
- Chun-Yung Sung
- Haizhou Yin
- et al.
- 2005
- IEDM 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
High performance and low power transistors integrated in 65nm bulk CMOS technology
- Z. Luo
- A. Steegen
- et al.
- 2004
- IEDM 2004
25 nm CMOS design considerations
- Y. Taur
- C. Wann
- et al.
- 1998
- IEDM 1998
RF perspective of sub-tenth-micron CMOS
- C. Wann
- L. Su
- et al.
- 1998
- ISSCC 1998
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1996
- IEDM 1996
High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1997
- IEEE Electron Device Letters
Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- K.Y. Lim
- V. Chan
- et al.
- 2005
- ESSDERC 2005
SRAM Cell Design for Stability Methodology
- Clement Wann
- Robert Wong
- et al.
- 2005
- VLSI Technology 2005