0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
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19 results for Michael Hargrove
Latchup in CMOS technology
- M. Hargrove
- S. Voldman
- et al.
- 1998
- IRPS 1998
History dependence of non-fully depleted (NFD) digital SOI circuits
- F. Assaderaghi
- G. Shahidi
- et al.
- 1996
- VLSI Technology 1996
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
Characterization of fast relaxation during BTI stress in conventional and advanced CMOS devices with HfO2 gate stacks
- Andreas Kerber
- Kingsuk Maitra
- et al.
- 2008
- IEEE Transactions on Electron Devices
Effect of thermal processing on strain relaxation and interdiffusion in Si/SiGe heterostructures studied using Raman spectroscopy
- S.J. Koester
- K. Rim
- et al.
- 2001
- Applied Physics Letters
RF potential of a 0.18-μm CMOS logic device technology
- Joachim N. Burghartz
- Michael Hargrove
- et al.
- 2000
- IEEE Transactions on Electron Devices
Shallow trench isolation double-diobe electrostatic discharge circuit and interaction with DRAM output circuitry
- Steven H. Voldman
- Vaughn P. Gross
- et al.
- 1993
- Journal of Electrostatics
Numerical Solution of the Semiconductor Transport Equations with Current Boundary Conditions
- Bertrand M. Grossman
- Michael J. Hargrove
- 1983
- IEEE T-ED