Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- X. Yu
- Oleg Gluschenkov
- et al.
- 2011
- IEDM 2011
Publications
Date
Featured collections
Popular topics
9 results for Ming Cai
Leakage and contact resistance reduction by diffusion of dopants in NiPt suicide
- Ahmet Ozcan
- Ming Cai
- et al.
- 2011
- ADMETA 2011
On the systematic analysis of ring-delay performance using statistical behavior model
- Q. Liang
- B. Greene
- et al.
- 2009
- ISDRS 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- M. Cai
- B. Greene
- et al.
- 2008
- IEEE International SOI Conference 2008
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
Advanced strain engineering for state-of-the-art nanoscale CMOS technology
- Bin Yang
- Ming Cai
- 2011
- Science China Information Sciences
Stress liner effects for 32-nm SOI MOSFETs with HKMG
- Ming Cai
- Karthik Ramani
- et al.
- 2010
- IEEE T-ED
Ring oscillator technique for MOSFET CV characterization
- Manjul Bhushan
- Mark B. Ketchen
- et al.
- 2008
- IEEE Trans Semicond Manuf