VDD scaling for FinFET logic and memory circuits: The impact of process variations and SRAM stability
- C.-H. Lin
- K. Das
- et al.
- 2006
- VLSI-TSA 2006
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20 results for K. Das
Ultralow-voltage minimum-energy CMOS
- Scott Hanson
- Bo Zhai
- et al.
- 2006
- IBM J. Res. Dev
High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2006
- VLSID/Embedded 2006
Ring oscillators for CMOS process tuning and variability control
- Manjul Bhushan
- Anne Gattiker
- et al.
- 2006
- IEEE Trans Semicond Manuf
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2005
- IEEE Transactions on Electron Devices
Analysis and design of digital CMOS circuits in hybrid SOI-epitaxial technology with different crystal orientations
- Koushik K. Das
- Shih-Hsien Lo
- et al.
- 2004
- IEEE International SOI Conference 2004
Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004
Nanoscale CMOS circuit leakage power reduction By Double-gate device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004
New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for Nano-Scale SOI Technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
- K. Das
- R.V. Joshi
- et al.
- 2003
- ISLPED 2003