Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- IEEE J-EDS
Publications
29 results for Christopher M. Breslin
Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- EUROSOI-ULIS 2015
Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2014
- IEDM 2014
Vertical III-V nanowire device integration on Si(100)
- Mattias Borg
- Heinz Schmid
- et al.
- 2014
- Nano Letters
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- Sarunya Bangsaruntip
- K. Balakrishnan
- et al.
- 2013
- IEDM 2013
200 mm wafer-scale integration of sub-20 nm sacrificial nanofluidic channels for manipulating and imaging single DNA molecules
- C. Wang
- S.W. Nam
- et al.
- 2013
- IEDM 2013
Carbon nanotube complementary wrap-gate transistors
- Aaron D. Franklin
- Siyuranga O. Koswatta
- et al.
- 2013
- Nano Letters
Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: Towards monolithic integration of nano-devices
- Pratyush Das Kanungo
- Heinz Schmid
- et al.
- 2013
- Nanotechnology
Stacking graphene channels in parallel for enhanced performance with the same footprint
- Aaron D. Franklin
- Satoshi Oida
- et al.
- 2013
- IEEE Electron Device Letters
Pattern transfer of directed self-assembly patterns for CMOS device applications
- Hsin-Yu Tsai
- Hiroyuki Miyazoe
- et al.
- 2013
- J. Micro/Nanolithogr. MEMS MOEMS